1. Field of the Invention
The present invention relates to a system-in-package (SIP) module with memory, and particularly to a SIP module that integrates a cache memory with an embedded dynamic random access memory (DRAM).
2. Description of the Prior Art
Generally speaking, memories are usually designed as standard memories which are independent from application logic integrated circuits (ICs) based on certain industry standard (e.g. Joint Electronic Device Engineering Council, JEDEC is the exemplary one). That is to say, the memories are designed typically as standard memories for various application logic ICs based on the certain industry standard, but not for predetermined application logic ICs.
In an application logic IC, the application logic IC needs a memory controller to control communication between a standard memory and the application logic IC. Because the memory controller needs to communicate with various different standard memories, the memory controller is usually designed to have suboptimal performance, efficiency, and/or cost to respond the various different standard memories.
However, memory manufacturers intend to provide known good die memories, so the application logic IC only needs to communicate with the known good die memories. Meanwhile, if the memory controller is still designed to have suboptimal performance, efficiency, and/or cost to respond the various different standard memories, a system-in-package (SIP) module which includes the application logic IC, the known good die memories, and the memory controller cannot maximize performance thereof.